Systems and methods for altering timing edges of an input signal

ABSTRACT

Systems for altering the timing of edges of an input signal for altering the position in time of timing edges of an input signal are disclosed. Such a system includes a differential amplifier having positive and negative inputs and outputs. The differential amplifier includes a symmetrical differential field effect transistor (FET) pair, each FET transistor of the pair having drain, source, and gate electrodes, wherein the source electrodes of the FET transistors are connected together. The differential amplifier also includes active loads coupled to the drain electrodes of the FET transistors and configured to be controllably biased to offset effects to the delay element caused by a plurality of operating variations. The delay element also includes variable capacitance banks connected to the outputs of the differential amplifier and configured to supply a selected capacitance to the outputs so as to delay and thereby alter the timing edges of the input signal. Methods and other systems also are provided.

FIELD OF THE INVENTION

[0001] The present invention generally relates to variable delaycircuits. More particularly, the present invention relates to systemsand methods for altering timing edges of an input signal.

DESCRIPTION OF THE RELATED ART

[0002] Many conventional discrete and gate array devices are used in theelectronics industry for adjusting the phase of digital signals. Phaseadjustment is typically accomplished by delaying the rising or fallingedge of a digital pulse. However, due to power supply, temperature,and/or manufacturing process variations, the delays produced by theseconventional devices may vary.

[0003] One such application in which inconsistent delay is unacceptableis in testing applications. By way of example, integrated circuits aretypically tested by applying test signals to the circuits and thenmonitoring the outputs of the circuits. Clearly, the accuracy of thetest signals is often critical so that an improper output can beattributed to the defects in the circuit and not to the test signal.Those variables listed above, such as temperature can degrade theaccuracy of the test signals and lead to inaccurate test results.

[0004] Based on the foregoing, it should be understood that there is aneed for improved systems and methods that address those and/or otherperceived shortcomings of the prior art.

SUMMARY OF THE INVENTION

[0005] A system in accordance with the invention for altering theposition in time of timing edges of an input signal includes adifferential amplifier having positive and negative inputs and outputs.The differential amplifier includes a symmetrical differential fieldeffect transistor (FET) pair, each FET transistor of the pair havingdrain, source, and gate electrodes, wherein the source electrodes of theFET transistors are connected together. The differential amplifier alsoincludes active loads coupled to the drain electrodes of the FETtransistors and configured to be controllably biased to offset effectsto the system caused by a plurality of operating variations. The systemalso includes variable capacitance bank connected to the outputs of thedifferential amplifier and configured to supply a selected capacitanceto the outputs so as to delay and thereby alter the timing edges of theinput signal.

[0006] The present invention may also be construed as a differentialamplifier having positive and negative inputs and outputs. Thedifferential amplifier includes a symmetrical differential field effecttransistor (FET) pair, each having drain, source, and gate electrodes,wherein the source electrodes of the FET transistors are connectedtogether and active loads coupled to the drain electrodes of the FETtransistors and configured to be controllably biased to offset effectsto the differential amplifier caused by a plurality of operatingvariations. The differential amplifier also includes a third FETtransistor coupled to the source electrodes of the FET differential pairand configured as an active current source. The third FET transistor isconfigured to be selectively biased to control an amount of currentpassing through the third FET transistor so as to further offset effectsto the differential amplifier caused by the plurality of operatingvariations.

[0007] A method in accordance with the present invention includes:providing an input signal and the compliment of the input signal to adelay element; varying a resistance of the delay element to offseteffects caused by a plurality of operating variations; and varying acapacitance of the delay element to provide for a discrete delay to theinput signal.

[0008] Clearly, some embodiments of the invention may addressshortcomings of the prior art in addition to, or in lieu of, thosedescribed here. Additionally, other systems, methods, features, andadvantages of the present invention will be or become apparent to onewith skill in the art upon examination of the following drawings anddetailed description. It is intended that all such additional systems,methods, features, and advantages be included within this description,be within the scope of the present invention, and be protected by theaccompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The invention can be better understood with reference to thefollowing drawings. The components in the drawings are not necessarilyto scale, emphasis instead being placed upon clearly illustrating theprinciples of the present invention. Moreover, in the drawings, likereference numerals designate corresponding parts throughout the severalviews.

[0010]FIG. 1 is a block diagram illustrating an embodiment of a testingsystem in accordance with the present invention.

[0011]FIG. 2 is a circuit schematic of an embodiment of a delay elementin accordance with the present invention.

[0012]FIG. 3 is a circuit schematic of a variable capacitance anembodiment of the delay element of FIG. 2.

[0013]FIG. 4 is a flowchart diagram illustrating an embodiment of amethod for altering timing edges of a signal in accordance with thepresent invention.

[0014]FIG. 5 is a flowchart further illustrating the method of FIG. 4.

[0015]FIG. 6 is a flowchart diagram illustrating another embodiment of amethod for effectively altering timing edges of a signal using theembodiment of the delay element of FIG. 2.

DETAILED DESCRIPTION

[0016] Systems and methods according to the present invention providevariable delays to input signals. As described in more detail below, thesystems and methods may be able to more accurately provide such variabledelays with regard to a variety of operating variations, such astemperature, supply voltage, and process variations than conventionalsystems.

[0017]FIG. 1 is a block diagram illustrating an embodiment of a testingsystem 1 in accordance with the present invention. The testing system 1generally includes a waveform generator 10 coupled to a device undertest (DUT) 15. The DUT 15 may be any electrical component to which atest signal may be provided. For example, the DUT 15 of FIG. 1 is anintegrated circuit (IC).

[0018] The waveform generator 10 includes a clock 20 coupled to N delayelements 50 a-50N. The delay elements 50 a-50N are collectively coupledto a formatter 30. The formatter 30 is depicted as being directlycoupled to the DUT 15, although indirect coupling via other componentscould be used. In practice, the waveform generator 10 may include othercomponents that may further shape and define a waveform such as gainstages, integrator circuits, and/or differentiating circuits. Theseelements may be used to create waveforms other than the standardwaveform typically produced by the clock 20, such as triangle waveformsand ramp waveforms. Although, in practice, these components would befound in most waveform generators 10, they have been excluded from thisexplanation for clarity. Those skilled in the art would appreciate thatthe components described in FIG. 1 suffice for a concise explanation.

[0019] In practice, the clock 20 provides a clock signal to each of thedelay elements 50 a-50N, where the clock signal is typically a squarewave with a particular period and amplitude. The clock signal generallyprovides for a symmetrical square wave. Testing with this symmetrical,pre-defined, periodic, square wave signal is limited. Manipulation ofthis signal may provide for more elaborate test signals.

[0020] In the embodiment of FIG. 1, 16 delay elements (N=16) 50 a-50Nreceive the clock signal from the clock 20. In other embodiments, adifferent number of delay elements 50 is provided. Generally, each delayelement 50 is pre-configured to provide for a different delay to theclock signal that is provided by the clock 20. It is important to note,aspects of the present invention require not only the clock signal to beprovided to a delay element 50 but also the exact compliment (theinverse) of the clock signal. This may require a simple inverter to beplaced in between the clock signal 20 and each of the delay elements 50a-50N. Alternatively, the clock 20 may produce an inverse to the clocksignal concurrently with the clock signal. The importance of having acomplimentary signal will become clear in later figures. Likewise, thestructure and function of a delay element 50 will be described in laterfigures.

[0021] The formatter 30 may be considered a programmable function blockthat builds the waveform. The formatter 30 is configured to receive theoutput signals from each of the delay elements 50 a-50N. Each outputsignal may be a different delayed representation of the original clocksignal. Furthermore, although not shown, other functional blocks may befound between the delay elements 50 a-50N and the formatter 30 such asgain amplifiers, inverters, etc. . The formatter 30 may be programmed toselect certain signals from certain selected delay elements 50 a-50N andthus provide one waveform to the DUT 15. The selected waveform is thusused as a stimulus signal to the DUT 15 to stimulate certain behaviorsof the DUT 15.

[0022] The waveform generator 10 would typically be found in some typeof automatic testing equipment (ATE). The ATE may include programmableinputs that may be provided to the delay elements 50 a-50N toselectively control the delay provided by each element. Other inputs ofthe ATE may be provided to the formatter 30 to choose and piece togethera single waveform from the collective delayed waveforms. ATEs are wellknown in the art and so no further explanation is provided.

[0023]FIG. 2 is a circuit schematic of a delay element 50 in accordancewith embodiments of the present invention. The delay element 50 may beconsidered any one of the delay elements 50 a-50N of the waveformgenerator 10 of FIG. 1. The delay element 50 may provide for apredetermined constant delay to an input signal. The delay provided tothe input signal may remain constant regardless of operating variationsthat would typically affect the delay provided to the input signal.Furthermore, the delay element 50 may be programmably configured duringoperation to provide a different delay.

[0024] The delay element 50 includes a differential amplifier 100 havinga positive input (IN⁺) 130 and a complimentary negative input (IN⁻) 135.Likewise, the differential amplifier 100 has a positive output (OUT⁺)140 and a complimentary negative output (OUT⁺) 145. The differentialamplifier 100 includes a symmetrical differential field effecttransistor (FET) pair 110 having field effect transistors 112 and 114.In this embodiment, the FET transistors 112 and 114 are be substantiallymatched so as to provide for symmetry in the differential amplifier 100.The required tolerance of transistor matching may be dictated by theapplication. Some applications use only every other edge, making thematching requirement much less important. Other applications may useeach edge and require an accuracy in which transistor matching is moreimportant. In these latter cases, a careful artwork realization mayinsure the matching is achieved to a sufficient tolerance. Otherwise,the matching is an intrinsic feature of the particular processtechnology used to implement the design in silicon. The design must betolerant of this intrinsic transistor mismatch.

[0025] In this embodiment, the FET transistors 112 and 114 are NMOStransistors where the sources of the transistors 112 and 114 are tiedtogether at a common node. The positive input 130 of the differentialamplifier 100 is coupled to the gate of the FET transistor 114 and,likewise, the negative input 135 of the differential amplifier 100 iscoupled to the gate of the second FET transistor 112 of the differentialpair 110. Certainly, vice-versa could be applied. In this case, theoutputs 140 and 145 would be switched. Again, this requires thedifferential amplifier 100 to be substantially balanced.

[0026] Two PMOS transistors 102 and 104 are coupled to the drains of theFET transistors 112 and 114 and serve to provide an active load on eachside of the differential amplifier 100. In this embodiment, the activeload PMOS transistors 102 and 104 are be biased in their linear region,thus serving as resistors. The sources of the active load FETtransistors 102 and 104 are coupled to a supply voltage, V_(DD). Thepositive output, OUT⁺, 140 is coupled to the drains of FET transistor112 and active load transistor 102 which are coupled together. Thenegative output, OUT⁻, 145 of the differential amplifier 100 is coupledto the drains of FET transistor 114 and active load FET transistor 104.

[0027] A tail current source provided by a fifth FET transistor 120 maybe coupled to the common sources of the symmetrical FET transistor pair110. The FET transistor 120 may be biased such that it remains in itssaturation region so as to serve as a tail current source to thedifferential amplifier 100.

[0028] A first control voltage, V₁, 150 is coupled to the gates of theactive load FET transistors 104 and 102 to variably control theconductance of the active load FET transistors 104 and 102. The variancein the conductance of the FET transistors 104 and 102 can controllablyvary the current I₁ passing through transistors 104 and 102 and onthrough to the outputs 140 and 145 of the differential amplifier 100.

[0029] A second control voltage, V₂, 155 may be provided to the gate ofthe tail FET transistor 120 to vary the conductance of the FETtransistor 120. The variance in the conductance of the FET transistor120 may vary the current 12 passing through the FET transistor 120.

[0030] A variable capacitance bank 200 is coupled to each of the outputs140 and 145 of the differential amplifier 100. The variable capacitancebank 200 will be described in further detail in FIG. 3, but generally iscomposed of several FET transistor banks that provide for incrementalcapacitance. The several FET transistor banks may be programmablyenabled with a digital input signal.

[0031] Having described the general structure of the delay element 50, adescription of the general operation of the delay element 50 will now bediscussed. As mentioned above, the delay element 50 includes adifferential amplifier 100. Like most differential amplifiers, thisdifferential amplifier 100 has a positive 130 and negative input 135 aswell as a positive 140 and negative output 145. It is preferred that thenegative input 135 be the true and accurate compliment of the positiveinput 130. In general, the input signals 130 and 135 would be digitalsignals having sufficient amplitudes so that the differential amplifier100 may have one transistor of the input pair 110 fully on and the otherfully off. The input signals 130 and 135, however, should not be toogreat in amplitude, because this may cause the two PMOS FET transistors102 and 104 to no longer operate in their linear regions. Ideally, aninput signal would have an upper limit of the positive supply voltage,V_(DD), and a lower limit of the positive supply voltage minus thethreshold voltage (V_(DD)−V_(T)) of one of the NMOS FET transistors,either 112 or 114.

[0032] Assuming, a well balanced differential amplifier, the negativeoutput 145 will be the compliment of the positive output 140. Thedifferential input pair 110 may receive the differential inputs 130 and135 via their respective gate electrodes. The differential outputs 140and 145 of the differential amplifier 100 are coupled to the drainelectrodes of the differential pair 110. The NMOS FET transistors 112and 114 would be continually biased in their saturation regions despitethe changing input signals 130 and 135.

[0033] The two PMOS FET transistors 102 and 104 are coupled to the drainelectrodes of the transistors 112 and 114 and serve to act as activeloads. The PMOS FET transistors 102 and 104 may be biased in theirlinear regions and so serve to act as variable resistances. The variableresistances of the PMOS FET transistors 102 and 104 are critical incontrolling the operating point of the differential amplifier 100, inthat they provide a controlled variable for the delay produced byamplifier 100. The PMOS FET transistors 102 and 104 may be biased with afirst control voltage 150, V₁, through their respective gate electrodes.By continuously biasing the PMOS FETs 102 and 104, a constant currentmay be supplied to the outputs of the differential amplifiers 100.

[0034] A third NMOS FET transistor 120 may be coupled to the sourceelectrodes of the NMOS FET transistors 112 and 114. The third NMOS FETtransistor 120 may be continually biased in its saturation region so asto act as a controllable current source. A second control voltage 155,V₂, may be coupled to the gate electrode of the transistor 120 tocontinually bias the transistor 120. A common current source in thedifferential amplifier 100 greatly helps in balancing the two sides ofthe differential amplifier 100 and so helps in reducing an imbalance inthe delay on the positive and negative timing edges (which can causepulse-width modulation). The transistor 120 also helps in maintaining anoperating current through the differential amplifier 100 that providesfor a desired operating point of the differential amplifier 100, mainlyin keeping the NMOS FET transistors 112 and 114 in saturation.

[0035] The two control voltages 150 and 155 may be provided by anexternal biasing circuit that can essentially offset operatingvariations on the differential amplifier 100. For example, temperatureoften can affect the performance of a FET transistor, and so thedifferential amplifier 100 is susceptible to temperature variations. Inparticular, the resistivity of the PMOS FET transistors 102 and 104 issubject to temperature variations, essentially because the carrierconcentration of the devices are a strong function of temperature. Theresistivity of the PMOS transistors 102 and 104 can also be controlledby the gate voltage, hence the first control voltage 150.

[0036] The supply voltage, V_(DD) may also vary and thus affect theperformance of the differential amplifier 100. Keeping everything elseconstant, variations in V_(DD) can affect the current passing throughthe PMOS transistors 102 and 104 and on to the outputs of thedifferential amplifier 100. Worse yet, a drastic change in V_(DD) cantake the PMOS transistors 102 and 104 out of the linear region. Thefirst control voltage 150 with the second control voltage 155 helps inmaintaining a constant current point throughout the differentialamplifier 100 despite changes in the supply voltage, V_(DD).

[0037] Process variations, another operating variation, can also affectthe performance of the differential amplifier 100, and thus theperformance of the delay element 50. Process variations may beconsidered variations in the physical aspects of the components of acircuit. For example, the width, W, and length, L, of any of thetransistors of the differential amplifier 100 may be slightly differentthan their nominal values. This affects the behavior of the transistorsat different operating points, but can be accounted for by the first andsecond control voltages 150 and 155.

[0038] Essentially, the delay on a signal induced by any amplifier is asubject of the amplifier's time constant, which is a function of itsresistance and capacitance. The first control voltage 150, inparticular, may be utilized to control a variable resistance (producedby the PMOS FET transistors 102 and 104) of the differential amplifier100. The variable capacitance banks 200 on each of the outputs of thedifferential amplifier 100 are thus used to control the capacitance ofthe differential amplifier 100. The general operation of the variablecapacitance banks 200 is discussed in further detail with reference toFIG. 3. In brief though, the variable capacitance banks 200 provide astepwise capacitance to the differential amplifier 100 which can finetune the desired delay on the signal. The variable capacitance banks 200are also a function of the output current provided at, the drainelectrodes of the PMOS and NMOS FET transistors. Control of the currentat the drain electrodes is important in controlling the charge providedto the variable capacitances 200.

[0039]FIG. 3 is a circuit schematic of a variable capacitance bank 200of the delay element 50 of FIG. 2. The variable capacitance bank 200generally provides for a programmable capacitance which serves toprovide a programmable delay to the signal. The variable capacitancebank 200 generally comprises several FET capacitor banks. The variablecapacitance bank 200 is disclosed in U.S. Pat. No. 5,283,631 (issuedFeb. 1, 1994) and incorporated by reference herein in its entirety.

[0040] A first capacitor bank 210 comprises one NMOS FET with its gateconnected in parallel to the output signal line 140 or 145 (See FIG. 2)as well as a short-circuited source-drain node which is controlled by agate-control input signal G1 on line 215 which is logically inverted andbuffered by an inverter 271. The input signal G1 is the leastsignificant bit (LSB) of the control word comprising input signalsG1-G5. A gate-control input signal G2 on line 225 is inverted andbuffered by an inverter 272 and controls the short-circuitedsource-drain node of a pair of parallel connected FETs forming thecapacitor bank 220. The capacitor bank 220 is connected to the outputsignal line 140 or 145 so as to control the next significant bit on theoutput signal line 140 or 145. A gate-control input signal G3 on line235, which is inverted by an inverter 273, controls a group of four FETsforming a capacitor bank 230, which is connected in parallel, via thegates of capacitor bank 230, to the output signal line 140 or 145 so asto control the next significant bit of the output signal line 140 or145. A logical NOR 274 of a gate-control input signal G4 on line 245 andgate-control input signal G5 on line 265 controls the source-drain nodeof a capacitor bank 240, comprising eight NMOS FETs, that provide thenext significant bit of delay to output signal line 140 or 145. Aninverter 275 provides an inverted output signal 255 of the gate-controlinput signal G4. Output signal 255 controls the source-drain node of acapacitor bank 250, comprising eight NMOS FETs that provide acapacitance delay for the next significant bit on the output signal line140 or 145. Gate-control input signals G4 and G5 are applied torespective inputs of a logical NAND 276. An output signal 267 of logicalNAND 276 controls the source-drain node of a capacitor bank 260. Thecapacitor bank 260 comprises eight NMOS FETs that provide a capacitancedelay for the MSB (Most Significant Bit) to output signal line 140 or145.

[0041] Note that the FET of the first four capacitor banks are arrangedin a binary fashion, (1, 2, 4, 8) so as to achieve the programmedcapacitance capabilities offered by a binary decode provided to inputsG1 through G3. The two MSBs, G4 and G5, are decoded in a thermometerfashion such that capacitor bank 250 consists of eight NMOS FETs insteadof the next binary equivalent of sixteen. The thermometer decode is suchthat the three 8 FET capacitor banks, 240, 250 and 260, turn onmonotonically as the input signal G4 and the input signal G5 increasefrom a binary zero (00 ₂) to a binary three (11 ₂).

[0042] In practice, the programmable variable capacitance is obtained bymodulating the gate-source-drain voltage (VGSS) of an NMOS FET whereVGSS means gate-to-source voltage with drain shorted to source. The gateof the NMOS FET of each capacitor bank 210, 220, 230, 240, 250 and 260is connected to the internal node of the buffer. The source and drainelectrodes are shorted together. The gate capacitance is effectivelyswitched in or out of the circuit by driving the source-drain node tothe negative or positive supply voltage, respectively. Thus, smallfinely controlled amounts of capacitance can be added to the internalnode via digital control. As is evident to those skilled in the art, thesize of the capacitor FET is chosen corresponding to the fine timingresolution required by an application of the present invention. Thenumber of capacitors attached to the internal node is determined by thedynamic range requirements. Since the delay of the element is linearlydependent on the capacitance of the internal node, this technique offersa linear relationship between the programmed capacitor setting and thedelay of the circuit. For the present invention, the higher ordercapacitors are implemented as capacitor banks 240, 250, and 260 in orderto reduce non-linearities.

[0043] The lower order capacitor banks 210, 220, and 230 (FET bankscomprised of less than 8 FETs) are rendered active by control signalsG1-G3. Once active, i.e., turned on, the transistors act like capacitorsand sink charge from the output signal line 140 or 145 to thereby delaya signal propagating from the output of the differential amplifier 100.Control signals G1-G3 are Boolean coded to apply additional capacitanceto the output signal line 140 or 145 in a linear fashion. The higherorder bits (FET banks comprised of 8 or more FETs) are rendered activeby control signals G4 and G5. The control signals G4 and G5 arethermometer encoded to minimize device mismatch due to processtolerances.

[0044] Collectively, the inverters 271, 272, 273, 275, NOR gate 274, andNAND gate 276 make up decode circuitry 270. The decode circuitry 270 mayreceive input control signals G1-G5 and subsequently drive the capacitorbanks 210-260. BY controlling the capacitance of the capacitor banks210-260 with the input control signals G1-G5, a precise control of thedelay produced by the variable capacitance bank 200 may be achieved.This helps in fine tuning the timing edges of the output signal of thedelay element 50.

[0045]FIG. 4 is a flowchart diagram illustrating a general method 300for altering timing edges of a signal in accordance with the presentinvention. The method 300 can be performed with a wide variety ofcircuit elements and devices. As will be discussed in subsequentflowcharts, the method will utilize components and elements similar tothose discussed in relation to FIGS. 2 and 3.

[0046] With regard to all flowcharts described herein, each blockrepresents a module, step, segment, or portion of the process. It shouldalso be noted that in some alternate implementations, the functionsnoted in the blocks may occur out of the order depicted. For example,two blocks shown in succession may in fact be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved.

[0047] The method 300 begins with providing a positive and negativeinput signal (step 300). The method proceeds with offsetting a pluralityof operating variations that can affect the manner in which the inputsignal is delayed (step 320). Offsetting the varying operatingvariations helps in maintaining a constant environment which isconducive for providing a predetermined delay to the signals (step 330).This predetermined delay may be of arbitrary resolution, but should bequite precise because of the constant operating environment created bystep 320.

[0048]FIG. 5 is a flowchart diagram illustrating an embodiment of amethod 350 for altering timing edges of a signal in accordance withembodiments of the present invention. The method 350 provides for a moredetailed description of how a delay signal may be generated byembodiments of the present invention. The method 350 may be implementedby a number of different circuit and/or devices, but preferably by thedelay element discussed in relation to FIG. 2. The method 350 canprovide for a judiciously chosen delay that is both accurate and stabledespite a variety of operating variations that can affect theperformance of the particular circuitry performing the delay operation

[0049] The method 350 begins with providing a positive and negativeinput signal to a delay element (step 360). The input signals should betrue compliments of each other and may be generated directly from asystem clock because it helps in balancing the delay element.

[0050] The next step is to vary the resistance of the delay element tooffset effects caused by a plurality of operating variations (step 370).These operating variations include: temperature variations; supplyvoltage variations; and/or process variations. Certainly other operatingvariations could affect the delay element as well. The resistance of thedelay element provides for a first variable in controlling the delayprovided by the delay element. Controlling the resistance helps incontrolling the current provided to the outputs of the delay element.

[0051] The final step in the method 350 is to vary the capacitance ofthe delay element so as to provide for a discrete delay to the signal(s)passing through the delay element (step 380). The capacitance of thedelay element, in this embodiment, is provided for by variablecapacitances (See FIGS. 2 and 3) at the outputs of the delay element.Essentially, the capacitance of the delay element controls the risingtimes and falling times of the of the output signal as it changes from alow to a high state and from a high to a low state. The rising andfalling times of the output signal determine the delay induced on theoutput signal. The variable capacitances as described in FIG. 3 canproduce a delay with great precision, provided the charging currentprovided to the capacitances remains constant. A constant current may bemaintained by controlling the resistance of the delay element.

[0052]FIG. 6 is a flowchart diagram illustrating a method 400 foreffectively and accurately altering the position in time of timing edgesof a signal in accordance with embodiments of the present invention. Themethod 400 begins with providing a delay element configured to performthe delay operation (step 410). The delay element may be similar todelay element 50 of FIG. 2, where a differential amplifier is configuredwith variable capacitance outputs. The variable capacitance outputs maybe programmed to provide a chosen delay to an input signal. Thedifferential amplifier may include active loads and an active tailcurrent source that may be continually biased to offset effects to thedifferential amplifier caused by operating variations. Examples ofoperating variations, as mentioned throughout, are temperaturevariation, supply voltage variation, and process variations to thecomponents of the differential amplifier and variable capacitance. Otheroperating variations may exist and may be accounted for by the delayelement 50.

[0053] The method 400 proceeds with providing an input signal and itscompliment to the delay element, particularly to the positive andnegative inputs of the differential amplifier of the delay element (step420). Once an input signal is provided to the delay element, the activeloads of the differential amplifier may be continuously biased tocontrol the current provided to differential outputs of the differentialamplifier. Controlling the current provided to the outputs of thedifferential amplifier controls the charging current that will beprovided to the variable capacitances at the output of the differentialamplifier. The charging current provided to the variable capacitancescontrol the delay induced by the variable capacitances on the signal tobe delayed. Biasing the active loads includes varying a bias voltage, V₁(step 435), which may be provided to the gates of two PMOS FETs actingas the active loads. The two PMOS FETs may be biased in their linearregions and so they emulate resistances. Varying the bias voltage, V₁,can vary the resistance of the PMOS FETs, and thus vary the currentpassing through them. The bias voltage, V₁, may be judiciously variedand provided to the active loads by a biasing circuit that is configuredto sense a plurality of process variations on the differentialamplifier. For example, temperature can greatly vary the carrierconcentration inside the PMOS FETs, which can vary the resistivity ofthe PMOS FETs. The bias voltage, V₁, can serve to offset the variationin resistivity induced by the variation in temperature. Essentially, thebiasing circuit may effectively sense the temperature variation andproduce the proper biasing voltage, V₁, to offset the sensed variation.

[0054] The method 400 proceeds with biasing the tail current source tocontrol the current passing through it (step 440). In this embodiment,the tail current source is an NMOS FET that may be biased with a secondbiasing voltage, V₂, supplied to the gate of the NMOS FET. Varying V₂ issimilar to varying V₁ to offset effects caused by various operatingvariations. Essentially, biasing V₁, and V₂ helps to keep a constantcurrent environment in the differential amplifier. A constant currentenvironment is critical to keeping the position of timing edges, andthus the delay in the signal, as constant and accurate as possiblethrough varying operating conditions. Although step 440 appears afterstep 430 in FIG. 5, it should be appreciated that these steps may beperformed concurrently. Properly biasing the active loads and the tailcurrent source may be performed constantly throughout operation of thedelay element.

[0055] The final step in method 400 is to program the variablecapacitance to provide for a desired delay on the signal (step 450).This step has been discussed in detail in relation to FIG. 3.Programming the variable capacitance may be considered providing for afine tuning of the timing edges, whereas biasing the active loads andthe tail current source may be considered coarse tuning. In the former,the fine tuning may be performed to accomplish a precise delay on asignal. In the latter, the coarse tuning may be utilized to provide adesired delay that remains constant, particularly when operatingvariations affect the performance of the delay element.

[0056] The foregoing description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit the invention to the precise forms disclosed. Modifications orvariations are possible in light of the above teachings. The embodimentor embodiments discussed, however, were chosen and described to provideillustration of the principles of the invention and its practicalapplication to thereby enable one of ordinary skill in the art toutilize the invention in various embodiments and with variousmodifications as are suited to the particular use contemplated.

[0057] By way of example, the methods described for programming thevariable capacitance banks may have comparable alternatives. In anotherregard, the delay elements have been included in a waveform generator toprovide an accurate programmable delay to a test waveform. Certainly,other utility may be found with the embodiments of the invention, inthat they generally provide for an accurate selectable delay. In otherwords, an accurate alteration of the timing edges of a signal isprovided. It should be appreciated by those skilled in the art that manyapplications for this type of element may be found. All suchmodifications and variations are within the scope of the invention asdetermined by the appended claims when interpreted in accordance withthe breadth to which they are fairly and legally entitled.

1. A system for altering the timing of edges of an input signal, thesystem comprising: a differential amplifier having positive and negativeinputs and outputs, the differential amplifier comprising: a symmetricaldifferential field effect transistor (FET) pair, each FET transistor ofthe pair having drain, source, and gate electrodes, wherein the sourceelectrodes of the FET transistors are connected together; and activeloads coupled to the drain electrodes of the FET transistors andconfigured to be controllably biased to offset effects to the systemcaused by a plurality of operating variations; and variable capacitancebanks connected to the outputs of the differential amplifier andconfigured to supply a selected capacitance to the outputs so as todelay and thereby alter the timing edges of the input signal.
 2. Thesystem of claim 1, wherein the differential amplifier further comprises:a third FET transistor coupled to the source electrodes of the FETdifferential pair and configured as an active current source, whereinthe third FET transistor is configured to be selectively biased tocontrol an amount of current passing through the third FET transistor soas to further offset effects to the system caused by the plurality ofoperating variations.
 3. The system of claim 2, wherein a first biasingvoltage is applied to the gate electrode of the third FET transistor soas to control a current passing through the third FET transistor.
 4. Thesystem of claim 2, wherein the plurality of operating variationsincludes any of the following: temperature variations, supply voltagevariations, and process variations.
 5. The system of claim 2, whereinthe third FET transistor is an NMOS FET transistor.
 6. The system ofclaim 1, wherein the plurality of operating variations includes any ofthe following: temperature variations, supply voltage variations, andprocess variations.
 7. The system of claim 1, wherein the active loadsof the differential amplifier each comprise: a PMOS FET transistorhaving drain, source, and gate electrodes, wherein the drain electrodeof the PMOS FET transistor of each active load is connected to the drainelectrode of each of the FET transistors of the FET transistor pair. 8.The system of claim 7, wherein a second biasing voltage is applied tothe gate electrode of the PMOS FET transistor of each active load so asto control a current passing through each of the PMOS FET transistors.9. The system of claim 1, wherein the FET transistors of the FETtransistor pair are NMOS FET transistors.
 10. The system of claim 1,wherein the variable capacitance banks comprise: decode circuitry fordecoding an input control word into at least one control signal; and atleast one capacitor bank coupled to the decode circuitry and to anoutput of the differential amplifier for applying a finite amount ofcapacitance to the output of the differential amplifier as a function ofthe at least one control signal.
 11. A differential amplifier havingpositive and negative inputs and outputs, the differential amplifiercomprising: a symmetrical differential field effect transistor (FET)pair, each having drain, source, and gate electrodes, wherein the sourceelectrodes of the FET transistors are connected together; active loadscoupled to the drain electrodes of the FET transistors and configured tobe controllably biased to offset effects to the differential amplifiercaused by a plurality of operating variations; and a third FETtransistor coupled to the source electrodes of the FET differential pairand configured as an active current source, wherein the third FETtransistor is configured to be selectively biased to control an amountof current passing through the third FET transistor so as to furtheroffset effects to the differential amplifier caused by the plurality ofoperating variations.
 12. The differential amplifier of claim 11,wherein the plurality of operating variations includes any of thefollowing: temperature variations, supply voltage variations, andprocess variations.
 13. The differential amplifier of claim 11, whereinthe active loads each comprise: a PMOS FET transistor having drain,source, and gate electrodes, wherein the drain electrode of the PMOS FETtransistor of each active load is connected to the drain electrode ofeach of the FET transistors of the FET transistor pair.
 14. Thedifferential amplifier of claim 13, wherein a first biasing voltage isapplied to the gate electrode of the PMOS FET transistor of each activeload so as to control a current passing through each PMOS FETtransistor.
 15. The differential amplifier of claim 14, wherein thecurrent passing through each PMOS FET transistor is controlled by thefirst biasing voltage controlling the resistivity of the PMOS FETtransistors.
 16. The differential amplifier of claim 11, wherein asecond biasing voltage is applied to the gate electrode of the third FETtransistor so as to control a current passing through the third FETtransistor.
 17. The differential amplifier of claim 16, wherein thethird FET transistor is an NMOS FET transistor.
 18. A method foraltering the timing edges of an input signal, the method comprising:providing an input signal and the compliment of the input signal to adelay element; varying a resistance of the delay element to offseteffects caused by a plurality of operating variations; and varying acapacitance of the delay element to provide for a discrete delay to theinput signal.
 19. The method of claim 18, wherein the step of varyingthe resistance comprises: properly biasing active loads of the delayelement and a tail FET transistor of the delay element, wherein the tailFET transistor acts as a controlled current source.
 20. The method ofclaim 19, wherein the active loads are PMOS FET transistors and whereinthe step of properly biasing comprises: providing a control voltage tothe gate electrodes of the PMOS FET transistors such that controlvoltage controls the resistance of the transistors and thus the currentflowing through the PMOS FET transistors.
 21. The method of claim 18,wherein the plurality of operating variations includes any of thefollowing: temperature variations, supply voltage variations, andprocess variations.